Crossbar memory systems are well regarded for their practicable implementation of a relatively dense aggregation of memory bits. Typically, crossbar memory systems include an array of constituent ‘memory cells,’ which themselves typically include a two-terminal memory device in conjunction with a ‘select device.’ The memory devices typically operate to store information states (e.g. a first information state and a second information state, as in a conventional binary system). The select devices generally operate to facilitate the ‘selection’ of particular memory devices for reading/writing operations. For example, select devices can operate to: limit leakage paths, improve read characteristics, and/or improve memory device selection. Conventionally, select devices have been realized using diodes and/or transistors.
Crossbar memory systems also generally include two sets of connection lines (e.g. a set of bit lines and a set of word lines), that are typically overlaid such that they cross one another so as to form a grid-like pattern; the constituent memory cells are typically disposed at the intersecting points of the connection lines such that each memory cell is electrically coupled to a unique combination of two connection lines. In this way, each memory cell can be separately operated (e.g. via the respective unique combination of connection lines).